Add xilinx fpga driver
This patch implemented Xilinx FPGA driver in cyborg. Currently can bind xilinx card to guest, and support programming. Implements: blueprint add-xilinx-fpga-driver Change-Id: I8cf48f64a0754ff13da2dddc4fabc601087b14b1
This commit is contained in:
ericxiett
parent
828fed561c
commit
2c2ab34ee3
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# Copyright 2021 Inspur, Inc.
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#
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# Licensed under the Apache License, Version 2.0 (the "License"); you may
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# not use this file except in compliance with the License. You may obtain
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# a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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# License for the specific language governing permissions and limitations
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# under the License.
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"""
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Cyborg Xilinx FPGA driver implementation.
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"""
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from oslo_concurrency import processutils
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from cyborg.accelerator.drivers.fpga.base import FPGADriver
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from cyborg.accelerator.drivers.fpga.xilinx import sysinfo
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from cyborg.common import exception
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import cyborg.privsep
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@cyborg.privsep.sys_admin_pctxt.entrypoint
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def _fpga_program_privileged(cmd_args):
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# Example: xbmgmt program --device 0000:d8:00.0
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# --base --image xilinx-u250-gen3x16-base
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cmd = ["/opt/xilinx/xrt/bin/xbmgmt"]
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cmd.extend(cmd_args)
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return processutils.execute(*cmd)
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class XilinxFPGADriver(FPGADriver):
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"""Class for Xilinx FPGA drivers.
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Vendor should implement their specific drivers in this class.
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"""
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VENDOR = "xilinx"
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def __init__(self, *args, **kwargs):
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pass
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def discover(self):
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return sysinfo.fpga_tree()
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def program(self, controlpath_id, image_file_path):
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"""Program the FPGA with the provided bitstream image.
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:param controlpath_id: the ID of controlpath.
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:param image_file_path: the path of the image file
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:returns: True on success, False on failure
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"""
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if controlpath_id['cpid_type'] != "PCI":
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raise exception.InvalidType(obj='controlpath_id',
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type=controlpath_id['cpid_type'],
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expected='PCI')
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cmd_args = ['program']
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cmd_args.append('--device')
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bdf_dict = controlpath_id['cpid_info']
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# BDF format: domain:bus:device:function
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bdf = ':'.join([s for s in map(lambda x: bdf_dict[x],
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['domain', 'bus', 'device', 'function'])])
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cmd_args.append(bdf)
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cmd_args.append('--base')
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cmd_args.append('--image')
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cmd_args.append(image_file_path)
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try:
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_fpga_program_privileged(cmd_args)
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return True
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except Exception:
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return False
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@ -0,0 +1,188 @@
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# Copyright 2021 Inspur, Inc.
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#
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# Licensed under the Apache License, Version 2.0 (the "License"); you may
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# not use this file except in compliance with the License. You may obtain
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# a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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# License for the specific language governing permissions and limitations
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# under the License.
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"""
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Cyborg Xilinx FPGA driver implementation.
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"""
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import re
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from oslo_concurrency import processutils
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from oslo_log import log as logging
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from oslo_serialization import jsonutils
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from cyborg.accelerator.common import utils
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from cyborg.common import constants
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from cyborg.conf import CONF
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from cyborg.objects.driver_objects import driver_attach_handle
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from cyborg.objects.driver_objects import driver_attribute
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from cyborg.objects.driver_objects import driver_controlpath_id
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from cyborg.objects.driver_objects import driver_deployable
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from cyborg.objects.driver_objects import driver_device
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from cyborg.privsep import sys_admin_pctxt
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LOG = logging.getLogger(__name__)
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XILINX_FPGA_FLAGS = ["Xilinx Corporation Device",
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"Processing accelerators"]
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XILINX_FPGA_INFO_PATTERN = re.compile(
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r"(?P<pci_addr>[0-9a-fA-F]{4}:[0-9a-fA-F]{2}:"
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r"[0-9a-fA-F]{2}\.[0-9a-fA-F]) "
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r"(?P<controller>.*) [\[].*]: (?P<model>.*) .*"
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r"[\[](?P<vendor_id>[0-9a-fA-F]"
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r"{4}):(?P<product_id>[0-9a-fA-F]{4})].*")
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XILINX_PF_MAPS = {"mgmt": "xclmgmt", "user": "xocl"}
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VENDOR_MAPS = {"10ee": "xilinx"}
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@sys_admin_pctxt.entrypoint
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def lspci_privileged(cmd):
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return processutils.execute(*cmd)
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def get_pci_devices(pci_flags, vendor_id=None):
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device_for_vendor_out = []
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all_device_out = []
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cmd = ['lspci', '-nnn', '-D']
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lspci_out = lspci_privileged(cmd)[0].split('\n')
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for i in range(len(lspci_out)):
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if all(x in lspci_out[i] for x in pci_flags):
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all_device_out.append(lspci_out[i])
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if vendor_id and vendor_id in lspci_out[i]:
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device_for_vendor_out.append(lspci_out[i])
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return device_for_vendor_out if vendor_id else all_device_out
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def _generate_traits(vendor_id, product_id):
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"""Generate traits for FPGAs.
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: param vendor_id: vendor_id of FPGA
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: param product_id: product_id of FPGA
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Example FPGA traits:
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{traits:["CUSTOM_FPGA_XILINX", "CUSTOM_FPGA_PRODUCT_ID_5001"]}
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"""
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traits = []
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traits.append("CUSTOM_FPGA_" + VENDOR_MAPS.get(vendor_id, "").upper())
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traits.append("CUSTOM_FPGA_PRODUCT_ID_" + product_id.upper())
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return {"traits": traits}
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def _get_pf_type(device):
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cmd = ['lspci', '-k', '-s', device]
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result = lspci_privileged(cmd)[0]
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for k, v in XILINX_PF_MAPS.items():
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if v in result:
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return k
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def _combine_device_by_pci_func(pci_devices):
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fpga_devices = []
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for pci_dev in pci_devices:
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m = XILINX_FPGA_INFO_PATTERN.match(pci_dev)
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if m:
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pci_dict = m.groupdict()
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LOG.debug('Xilinx fpga pci device in dict: %s', pci_dict)
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# 0000:3b:00.0/1
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is_existed = False
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new_addr = pci_dict.get('pci_addr')
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for fpga in fpga_devices:
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existed_addr = fpga.get('pci_addr')[0]
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# compare domain:bus:slot
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if existed_addr and \
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new_addr.split('.')[0] == existed_addr.split('.')[0]:
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fpga.update({'pci_addr': [existed_addr, new_addr]})
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is_existed = True
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if not is_existed:
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traits = _generate_traits(pci_dict["vendor_id"],
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pci_dict["product_id"])
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pci_dict["rc"] = constants.RESOURCES["FPGA"]
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pci_dict.update(traits)
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pci_dict.update({'pci_addr': [new_addr]})
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fpga_devices.append(pci_dict)
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return fpga_devices
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def _generate_controlpath_id(fpga):
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driver_cpid = driver_controlpath_id.DriverControlPathID()
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driver_cpid.cpid_type = "PCI"
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driver_cpid.cpid_info = utils.pci_str_to_json(fpga['pci_addr'][0])
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return driver_cpid
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def _generate_dep_list(fpga):
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dep_list = []
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driver_dep = driver_deployable.DriverDeployable()
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driver_dep.attribute_list = _generate_attribute_list(fpga)
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driver_dep.attach_handle_list = []
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driver_dep.name = CONF.host + '_' + fpga["pci_addr"][0]
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driver_dep.driver_name = VENDOR_MAPS.get(fpga["vendor_id"]).upper()
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driver_dep.num_accelerators = 1
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driver_dep.attach_handle_list = _generate_attach_handle(fpga)
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dep_list.append(driver_dep)
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return dep_list
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def _generate_attribute_list(fpga):
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attr_list = []
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for k, v in fpga.items():
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if k == "rc":
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driver_attr = driver_attribute.DriverAttribute()
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driver_attr.key, driver_attr.value = k, v
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attr_list.append(driver_attr)
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if k == "traits":
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values = fpga.get(k, [])
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for index, val in enumerate(values):
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driver_attr = driver_attribute.DriverAttribute(
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key="trait" + str(index), value=val)
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attr_list.append(driver_attr)
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return attr_list
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def _generate_attach_handle(fpga):
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driver_ahs = []
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for addr in fpga.get('pci_addr'):
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driver_ah = driver_attach_handle.DriverAttachHandle()
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driver_ah.attach_type = constants.AH_TYPE_PCI
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driver_ah.attach_info = utils.pci_str_to_json(addr)
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driver_ah.in_use = False
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driver_ahs.append(driver_ah)
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return driver_ahs
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def fpga_tree():
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fpga_list = []
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fpga_pci_devices = get_pci_devices(XILINX_FPGA_FLAGS)
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LOG.debug("Xilinx fpga devices from lspci: %s", fpga_pci_devices)
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# In the return pci devices, mgmt pf and user pf are two entries.
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# Now only when binding both to vm, end user can program it.
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# So combine these two entries into one device.
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for fpga in _combine_device_by_pci_func(fpga_pci_devices):
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driver_device_obj = driver_device.DriverDevice()
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driver_device_obj.vendor = fpga["vendor_id"]
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driver_device_obj.model = fpga.get('model', 'miss model info')
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std_board_info = {'product_id': fpga.get('product_id', None),
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'controller': fpga.get('controller', None)}
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vendor_board_info = {
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'vendor_info': fpga.get('vendor_info', 'fpga_vb_info')}
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driver_device_obj.std_board_info = jsonutils.dumps(std_board_info)
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driver_device_obj.vendor_board_info = \
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jsonutils.dumps(vendor_board_info)
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driver_device_obj.type = constants.DEVICE_FPGA
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driver_device_obj.stub = fpga.get('stub', False)
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driver_device_obj.controlpath_id = _generate_controlpath_id(fpga)
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driver_device_obj.deployable_list = _generate_dep_list(fpga)
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fpga_list.append(driver_device_obj)
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return fpga_list
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@ -135,9 +135,18 @@ class ARQsController(base.CyborgController):
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extarq_list = []
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for group_id, group in enumerate(devprof.groups):
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accel_resources = [
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int(val) for key, val in group.items()
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if key.startswith('resources')]
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accel_resources = []
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# If the device profile requires the Xilinx fpga, the number of
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# resources should multiply by 2 cause that end user can program
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# the device only when both MGMT and USER PF are bound to
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# instance.
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if group.get("trait:CUSTOM_FPGA_XILINX") == "required":
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accel_resources = [int(group.get("resources:FPGA"))] * 2
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else:
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accel_resources = [
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int(val) for key, val in group.items()
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if key.startswith('resources')]
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# If/when we introduce non-accelerator resources, like
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# device-local memory, the key search above needs to be
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# made specific to accelerator resources only.
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@ -15,6 +15,7 @@
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from cyborg.accelerator.drivers.fpga.base import FPGADriver
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from cyborg.accelerator.drivers.fpga.intel.driver import IntelFPGADriver # noqa
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from cyborg.accelerator.drivers.fpga.inspur.driver import InspurFPGADriver # noqa
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from cyborg.accelerator.drivers.fpga.xilinx.driver import XilinxFPGADriver # noqa
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from cyborg.tests import base
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@ -22,7 +23,8 @@ class TestFPGADriver(base.TestCase):
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def test_create(self):
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FPGADriver.create("intel")
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FPGADriver.create("inspur")
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self.assertRaises(LookupError, FPGADriver.create, "xilinx")
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FPGADriver.create("xilinx")
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self.assertRaises(LookupError, FPGADriver.create, "fake")
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def test_discover(self):
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d = FPGADriver()
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@ -0,0 +1,129 @@
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# Copyright 2021 Inspur, Inc.
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#
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# Licensed under the Apache License, Version 2.0 (the "License"); you may
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# not use this file except in compliance with the License. You may obtain
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# a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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# License for the specific language governing permissions and limitations
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# under the License.
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from oslo_serialization import jsonutils
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from unittest import mock
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from cyborg.accelerator.drivers.fpga.xilinx.driver import XilinxFPGADriver
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from cyborg.tests import base
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XILINX_FPGA_INFO = ["0000:3b:00.0 Processing accelerators [1200]: "
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"Xilinx Corporation Device [10ee:5000]\n"
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"0000:3b:00.1 Processing accelerators [1200]: "
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"Xilinx Corporation Device [10ee:5001]"]
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def fake_output(arg):
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if arg == ['lspci', '-nnn', '-D']:
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return XILINX_FPGA_INFO
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class TestXilinxFPGADriver(base.TestCase):
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def setUp(self):
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super(TestXilinxFPGADriver, self).setUp()
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@mock.patch('cyborg.accelerator.drivers.fpga.'
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'xilinx.sysinfo.lspci_privileged')
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def test_discover(self, mock_devices_for_vendor):
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mock_devices_for_vendor.side_effect = fake_output
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self.set_defaults(host='fake-host', debug=True)
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fpga_list = XilinxFPGADriver().discover()
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self.assertEqual(1, len(fpga_list))
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attach_handle_list = [
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{'attach_type': 'PCI',
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'attach_info': '{"bus": "3b", '
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'"device": "00", '
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'"domain": "0000", '
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'"function": "0"}',
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'in_use': False},
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{'attach_type': 'PCI',
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'attach_info': '{"bus": "3b", '
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'"device": "00", '
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'"domain": "0000", '
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'"function": "1"}',
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'in_use': False}
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]
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attribute_list = [
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{'key': 'rc', 'value': 'FPGA'},
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{'key': 'trait0', 'value': 'CUSTOM_FPGA_XILINX'},
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{'key': 'trait1', 'value': 'CUSTOM_FPGA_PRODUCT_ID_5000'},
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]
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expected = {
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'vendor': '10ee',
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'type': 'FPGA',
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'std_board_info': {"controller": "Processing accelerators",
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"product_id": "5000"},
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'vendor_board_info': {"vendor_info": "fpga_vb_info"},
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'deployable_list':
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[
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{
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'num_accelerators': 1,
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'driver_name': 'XILINX',
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'name': 'fake-host_0000:3b:00.0',
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'attach_handle_list': attach_handle_list,
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'attribute_list': attribute_list
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},
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],
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'controlpath_id': {'cpid_info': '{"bus": "3b", '
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'"device": "00", '
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'"domain": "0000", '
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'"function": "0"}',
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'cpid_type': 'PCI'}
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}
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fpga_obj = fpga_list[0]
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fpga_dict = fpga_obj.as_dict()
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fpga_dep_list = fpga_dict['deployable_list']
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fpga_attach_handle_list = (
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fpga_dep_list[0].as_dict()['attach_handle_list'])
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fpga_attribute_list = fpga_dep_list[0].as_dict()['attribute_list']
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attri_obj_data = []
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[attri_obj_data.append(attr.as_dict()) for attr in fpga_attribute_list]
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attribute_actual_data = sorted(attri_obj_data, key=lambda i: i['key'])
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self.assertEqual(expected['vendor'], fpga_dict['vendor'])
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self.assertEqual(expected['controlpath_id'],
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fpga_dict['controlpath_id'])
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self.assertEqual(expected['std_board_info'],
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jsonutils.loads(fpga_dict['std_board_info']))
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self.assertEqual(expected['vendor_board_info'],
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jsonutils.loads(fpga_dict['vendor_board_info']))
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self.assertEqual(expected['deployable_list'][0]['num_accelerators'],
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fpga_dep_list[0].as_dict()['num_accelerators'])
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self.assertEqual(expected['deployable_list'][0]['name'],
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fpga_dep_list[0].as_dict()['name'])
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self.assertEqual(expected['deployable_list'][0]['driver_name'],
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fpga_dep_list[0].as_dict()['driver_name'])
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self.assertEqual(2, len(fpga_attach_handle_list))
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self.assertEqual(attach_handle_list[0],
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fpga_attach_handle_list[0].as_dict())
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self.assertEqual(attach_handle_list[1],
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||||
fpga_attach_handle_list[1].as_dict())
|
||||
self.assertEqual(attribute_list, attribute_actual_data)
|
||||
|
||||
@mock.patch('cyborg.accelerator.drivers.fpga.xilinx.driver.'
|
||||
'_fpga_program_privileged')
|
||||
def test_program(self, mock_prog):
|
||||
bdf = '0000:3b:00:0'
|
||||
expect_cmd_args = ['program', '--device', bdf, '--base',
|
||||
'--image', '/path/image']
|
||||
|
||||
xilinx_driver = XilinxFPGADriver()
|
||||
cpid_info = {"domain": "0000", "bus": "3b",
|
||||
"device": "00", "function": "0"}
|
||||
cpid = {'cpid_type': 'PCI', 'cpid_info': cpid_info}
|
||||
|
||||
# program PF
|
||||
mock_prog.return_value = bytes([0])
|
||||
xilinx_driver.program(cpid, "/path/image")
|
||||
mock_prog.assert_called_with(expect_cmd_args)
|
||||
|
|
@ -203,6 +203,26 @@ class TestARQsController(v2_test.APITestV2):
|
|||
dp_group_id = idx
|
||||
self.assertEqual(dp_group_id, out_arq['device_profile_group_id'])
|
||||
|
||||
@mock.patch('cyborg.objects.DeviceProfile.get_by_name')
|
||||
@mock.patch('cyborg.conductor.rpcapi.ConductorAPI.arq_create')
|
||||
def test_create_with_xilinx_fpga(self, mock_obj_extarq, mock_obj_dp):
|
||||
xilinx_fpga_dp = fake_device_profile.get_xilinx_fpga_devprof()
|
||||
mock_obj_dp.return_value = dp = xilinx_fpga_dp
|
||||
fake_xilinx_fpga_objs = fake_extarq.get_fake_xilinx_fpga_extarq_objs()
|
||||
mock_obj_extarq.side_effect = fake_xilinx_fpga_objs
|
||||
params = {'device_profile_name': dp['name']}
|
||||
response = self.post_json(self.ARQ_URL, params, headers=self.headers)
|
||||
data = jsonutils.loads(response.__dict__['controller_output'])
|
||||
out_arqs = data['arqs']
|
||||
|
||||
self.assertEqual(HTTPStatus.CREATED, response.status_int)
|
||||
self.assertEqual(len(out_arqs), 2)
|
||||
for in_extarq, out_arq in zip(fake_xilinx_fpga_objs, out_arqs):
|
||||
self._validate_arq(in_extarq.arq, out_arq)
|
||||
for idx, out_arq in enumerate(out_arqs):
|
||||
dp_group_id = idx
|
||||
self.assertEqual(dp_group_id, out_arq['device_profile_group_id'])
|
||||
|
||||
@mock.patch('cyborg.objects.DeviceProfile.get_by_name')
|
||||
@mock.patch('cyborg.objects.ExtARQ.create')
|
||||
def test_create_with_wrong_dp(self, mock_obj_extarq, mock_obj_dp):
|
||||
|
|
|
|||
|
|
@ -106,3 +106,23 @@ def get_db_devprofs():
|
|||
dp_list = _get_device_profiles_as_dict()
|
||||
db_devprofs = list(map(_convert_to_db_devprof, dp_list))
|
||||
return db_devprofs
|
||||
|
||||
|
||||
def get_xilinx_fpga_devprof():
|
||||
xilinx_fpga_dp = {
|
||||
"id": 3,
|
||||
"uuid": "638828d7-7145-4060-904c-894aa726b133",
|
||||
"name": 'fake_xilinx_fpga_dp',
|
||||
"description": "fake_xilinx_fpga_dp-desc",
|
||||
"created_at": datetime.datetime(
|
||||
2022, 1, 22, 10, 40, 56,
|
||||
tzinfo=datetime.timezone.utc),
|
||||
"updated_at": None,
|
||||
"groups": [
|
||||
{"resources:FPGA": "1",
|
||||
"trait:CUSTOM_FPGA_XILINX": "required",
|
||||
"trait:CUSTOM_FPGA_PRODUCT_ID_5000": "required",
|
||||
},
|
||||
]
|
||||
}
|
||||
return _convert_to_obj(xilinx_fpga_dp)
|
||||
|
|
|
|||
|
|
@ -300,3 +300,47 @@ def get_patch_list(same_device=True):
|
|||
'value': dev_uuid}
|
||||
patch_list[newarq['uuid']] = [host_binding, inst_binding, dev_binding]
|
||||
return patch_list, device_rp_uuid
|
||||
|
||||
|
||||
def get_fake_xilinx_fpga_extarq_objs():
|
||||
arqs = [
|
||||
{"uuid": 'b8c19eb2-e03c-47b4-b7cf-ced6086b2d11',
|
||||
"device_profile_group_id": 0,
|
||||
"state": "Initial",
|
||||
"device_profile_name": "fake_xilinx_fpga_dp",
|
||||
"hostname": "myhost",
|
||||
"instance_uuid": "5922a70f-1e06-4cfd-88dd-a332120d7144",
|
||||
"attach_handle_type": "PCI",
|
||||
# attach_handle info should vary across ARQs but ignored for testing
|
||||
"attach_handle_info": {
|
||||
"bus": "3b",
|
||||
"device": "00",
|
||||
"domain": "0000",
|
||||
"function": "0"
|
||||
},
|
||||
"device_profile_group": {
|
||||
"trait:CUSTOM_FPGA_XILINX": "required",
|
||||
"resources:FPGA": "1",
|
||||
"trait:CUSTOM_FPGA_PRODUCT_ID_5000": "required"}
|
||||
},
|
||||
{"uuid": '012955c7-90f9-45a9-bb7d-7c2907d8997f',
|
||||
"device_profile_group_id": 1,
|
||||
"state": "Initial",
|
||||
"device_profile_name": "fake_xilinx_fpga_dp",
|
||||
"hostname": "myhost",
|
||||
"instance_uuid": "5922a70f-1e06-4cfd-88dd-a332120d7144",
|
||||
"attach_handle_type": "PCI",
|
||||
# attach_handle info should vary across ARQs but ignored for testing
|
||||
"attach_handle_info": {
|
||||
"bus": "3b",
|
||||
"device": "00",
|
||||
"domain": "0000",
|
||||
"function": "1"
|
||||
},
|
||||
"device_profile_group": {
|
||||
"trait:CUSTOM_FPGA_XILINX": "required",
|
||||
"resources:FPGA": "1",
|
||||
"trait:CUSTOM_FPGA_PRODUCT_ID_5000": "required"}
|
||||
},
|
||||
]
|
||||
return list(map(_convert_from_dict_to_obj, arqs))
|
||||
|
|
|
|||
|
|
@ -0,0 +1,6 @@
|
|||
---
|
||||
features:
|
||||
- |
|
||||
Add the Xilinx FPGA driver. Through this driver Cyborg can manage Xilinx
|
||||
FPGA devices, including discovering devices' info and programming
|
||||
``xclbin``.
|
||||
|
|
@ -49,6 +49,7 @@ cyborg.database.migration_backend =
|
|||
cyborg.accelerator.driver =
|
||||
intel_fpga_driver = cyborg.accelerator.drivers.fpga.intel.driver:IntelFPGADriver
|
||||
inspur_fpga_driver = cyborg.accelerator.drivers.fpga.inspur.driver:InspurFPGADriver
|
||||
xilinx_fpga_driver = cyborg.accelerator.drivers.fpga.xilinx.driver:XilinxFPGADriver
|
||||
nvmf_spdk_driver = cyborg.accelerator.drivers.spdk.nvmf.nvmf:NVMFDRIVER
|
||||
nvidia_gpu_driver = cyborg.accelerator.drivers.gpu.nvidia.driver:NVIDIAGPUDriver
|
||||
fake_driver = cyborg.accelerator.drivers.fake:FakeDriver
|
||||
|
|
|
|||
Loading…
Reference in New Issue