openstack/cyborg
Code Issues Proposed changes

Merge "Improve the accuracy of device profile API responses in docs"

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This commit is contained in:
Zuul
2020-03-26 03:34:42 +00:00
committed by Gerrit Code Review
parent 31d23b7315 0bf59df4ad
commit fee057d8bb
3 changed files with 34 additions and 26 deletions
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16
doc/api_samples/device_profiles/device_profiles-create-resp.json
View File

@@ -1,11 +1,6 @@
{ {
"links":[
{
"href":"http://192.168.23.76/accelerator/v2/device_profiles/1a939c88-0b01-408b-bab0-4c61d3a02d71",
"rel":"self"
}
],
"name":"afexample_3", "name":"afexample_3",
"uuid":"1a939c88-0b01-408b-bab0-4c61d3a02d71",
"groups":[ "groups":[
{ {
"trait:CUSTOM_FUNCTION_ID_3AFB":"required", "trait:CUSTOM_FUNCTION_ID_3AFB":"required",
@@ -13,5 +8,12 @@
"trait:CUSTOM_FPGA_1":"required" "trait:CUSTOM_FPGA_1":"required"
} }
], ],
"uuid":"1a939c88-0b01-408b-bab0-4c61d3a02d71" "created_at": "2020-03-09 11:26:05+00:00",
"updated_at": null,
"links":[
{
"href":"http://192.168.23.76/accelerator/v2/device_profiles/1a939c88-0b01-408b-bab0-4c61d3a02d71",
"rel":"self"
}
]
} }

16
doc/api_samples/device_profiles/device_profiles-getone-resp.json
View File

@@ -1,12 +1,7 @@
{ {
"device_profile":{ "device_profile":{
"links":[
{
"href":"http://192.168.32.217/accelerator/v2/device_profiles/5518a925-1c2c-49a2-a8bf-0927d9456f3e",
"rel":"self"
}
],
"name":"fpga-dp1", "name":"fpga-dp1",
"uuid":"5518a925-1c2c-49a2-a8bf-0927d9456f3e",
"groups":[ "groups":[
{ {
"trait:CUSTOM_CHENKE_TRAITS":"required", "trait:CUSTOM_CHENKE_TRAITS":"required",
@@ -14,6 +9,13 @@
"accel:bitstream_id":"d5ca2f11-3108-4426-a11c-a959987565df" "accel:bitstream_id":"d5ca2f11-3108-4426-a11c-a959987565df"
} }
], ],
"uuid":"5518a925-1c2c-49a2-a8bf-0927d9456f3e" "created_at": "2020-03-09 11:26:05+00:00",
"updated_at": null,
"links":[
{
"href":"http://192.168.32.217/accelerator/v2/device_profiles/5518a925-1c2c-49a2-a8bf-0927d9456f3e",
"rel":"self"
}
]
} }
} }

28
doc/api_samples/device_profiles/device_profiles-list-resp.json
View File

@@ -1,29 +1,26 @@
{ {
"device_profiles":[ "device_profiles":[
{ {
"links":[
{
"href":"http://192.168.32.217/accelerator/v2/device_profiles/3d03fa5b-507c-4810-a344-759e9ef4337a",
"rel":"self"
}
],
"name":"bym-1", "name":"bym-1",
"uuid":"3d03fa5b-507c-4810-a344-759e9ef4337a",
"groups":[ "groups":[
{ {
"resources:FPGA":"1", "resources:FPGA":"1",
"trait:CUSTOM_FPGA_C260":"required" "trait:CUSTOM_FPGA_C260":"required"
} }
], ],
"uuid":"3d03fa5b-507c-4810-a344-759e9ef4337a" "created_at": "2020-03-09 11:26:05+00:00",
}, "updated_at": null,
{
"links":[ "links":[
{ {
"href":"http://192.168.32.217/accelerator/v2/device_profiles/5518a925-1c2c-49a2-a8bf-0927d9456f3e", "href":"http://192.168.32.217/accelerator/v2/device_profiles/3d03fa5b-507c-4810-a344-759e9ef4337a",
"rel":"self" "rel":"self"
} }
], ]
},
{
"name":"fpga-dp1", "name":"fpga-dp1",
"uuid":"5518a925-1c2c-49a2-a8bf-0927d9456f3e",
"groups":[ "groups":[
{ {
"trait:CUSTOM_CHENKE_TRAITS":"required", "trait:CUSTOM_CHENKE_TRAITS":"required",
@@ -31,7 +28,14 @@
"accel:bitstream_id":"d5ca2f11-3108-4426-a11c-a959987565df" "accel:bitstream_id":"d5ca2f11-3108-4426-a11c-a959987565df"
} }
], ],
"uuid":"5518a925-1c2c-49a2-a8bf-0927d9456f3e" "created_at": "2020-03-10 03:52:15+00:00",
"updated_at": null,
"links":[
{
"href":"http://192.168.32.217/accelerator/v2/device_profiles/5518a925-1c2c-49a2-a8bf-0927d9456f3e",
"rel":"self"
}
]
} }
] ]
} }