347 lines
12 KiB
Python
347 lines
12 KiB
Python
# Copyright 2019 Intel Inc.
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#
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# Licensed under the Apache License, Version 2.0 (the "License"); you may
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# not use this file except in compliance with the License. You may obtain
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# a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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# License for the specific language governing permissions and limitations
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# under the License.
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from cyborg.objects import arq
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from cyborg.objects import ext_arq
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from cyborg.objects.extarq import fpga_ext_arq
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def _get_arqs_as_dict():
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common = {
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"state": "Bound",
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"device_profile_name": "dp_example_1",
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"hostname": "myhost",
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"instance_uuid": "5922a70f-1e06-4cfd-88dd-a332120d7144",
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"attach_handle_type": "PCI",
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# attach_handle info should vary across ARQs but ignored for testing
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"attach_handle_info": {
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"bus": "1",
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"device": "0",
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"domain": "0",
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"function": "0"
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},
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"device_profile_group": {
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"trait:CUSTOM_FPGA_INTEL": "required",
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"resources:FPGA": "1",
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"accel:bitstream_id": "b069d97a-010a-4057-b70d-eca2b337fc9c"}
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}
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dp_groups = [
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{"device_profile_group": {"resources:GPU": "1"}},
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{"device_profile_group": {
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"trait:CUSTOM_FPGA_INTEL": "required",
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"resources:FPGA": "1"}},
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{"device_profile_group": {
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"trait:CUSTOM_FPGA_INTEL": "required",
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"resources:FPGA": "1",
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"accel:bitstream_id": "b069d97a-010a-4057-b70d-eca2b337fc9c"}},
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{"device_profile_group": {
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"trait:CUSTOM_FPGA_INTEL": "required",
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"resources:FPGA": "1",
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"accel:function_id": "25453786-03e0-4ee7-a640-969eb5a5aa44"}},
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{"device_profile_group": {
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"trait:CUSTOM_FPGA_INTEL": "required",
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"resources:FPGA": "1",
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"accel:bitstream_id": "b069d97a-010a-4057-b70d-eca2b337fc9c",
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"accel:function_id": "25453786-03e0-4ee7-a640-969eb5a5aa44"}},
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]
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arqs = [ # Corresponds to 1st device profile in fake_device)profile.py
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{"uuid": "a097fefa-da62-4630-8e8b-424c0e3426dc",
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"device_profile_group_id": 0,
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"device_rp_uuid": "8787595e-9954-49f8-b5c1-cdb55b59062f",
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},
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{"uuid": "aa140114-4869-45ea-8213-45f530804b0f",
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"device_profile_group_id": 1,
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"device_rp_uuid": "a1ec17f2-0051-4737-bac4-f074d8a01a9c",
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},
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{"uuid": "292b2fa2-0831-484c-aeac-09c794428a5d",
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"device_profile_group_id": 2,
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"device_rp_uuid": "a1ec17f2-0051-4737-bac4-f074d8a01a9c",
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},
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{"uuid": "3049ad04-a2b1-40a3-b9c8-480a5e661645",
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"device_profile_group_id": 3,
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"device_rp_uuid": "57455a49-bde4-490e-9179-9aa84a3870bb",
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},
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{"uuid": "3a9a07e7-d126-47a5-bf11-dcc04f9e60ff",
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"device_profile_group_id": 4,
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"device_rp_uuid": "fbd485e1-40b1-4a7e-84b9-f6b6959114a4",
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},
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]
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new_arqs = []
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for idx, new_arq in enumerate(arqs):
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common.update(dp_groups[idx])
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new_arq.update(common)
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new_arq.update(id=idx)
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new_arqs.append(new_arq)
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return new_arqs
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def _get_arqs_resloved_as_dict():
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arqs = [ # Corresponds to 1st device profile in fake_device)profile.py
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{"uuid": 'a097fefa-da62-4630-8e8b-424c0e3426dd',
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"device_profile_group_id": 0,
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"state": "Initial",
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"device_profile_name": "dp_example_1",
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"device_rp_uuid": None,
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"hostname": None,
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"instance_uuid": None,
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"attach_handle_type": None,
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# attach_handle info should vary across ARQs but ignored for testing
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"attach_handle_info": {},
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"device_profile_group": {}
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},
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{"uuid": 'aa140114-4869-45ea-8213-45f530804b0e',
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"device_profile_group_id": 1,
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"device_rp_uuid": "fbd485e1-40b1-4a7e-84b9-f6b6959114a5",
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"state": "Bound",
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"device_profile_name": "dp_example_1",
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"hostname": "myhost",
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"instance_uuid": "5922a70f-1e06-4cfd-88dd-a332120d7144",
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"attach_handle_type": "PCI",
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# attach_handle info should vary across ARQs but ignored for testing
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"attach_handle_info": {
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"bus": "1",
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"device": "0",
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"domain": "0",
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"function": "0"
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},
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"device_profile_group": {
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"trait:CUSTOM_FPGA_INTEL": "required",
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"resources:FPGA": "1",
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"accel:bitstream_id": "b069d97a-010a-4057-b70d-eca2b337fc9c"}
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},
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]
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new_arqs = []
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for idx, new_arq in enumerate(arqs):
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new_arq.update(id=idx)
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new_arqs.append(new_arq)
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return new_arqs
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def _get_arqs_bind_as_dict():
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common = [
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{
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"state": "Bound",
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"device_profile_name": "dp_example_1",
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"hostname": "myhost1",
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"instance_uuid": "5922a70f-1e06-4cfd-88dd-a332120d7144",
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"attach_handle_type": "PCI",
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# attach_handle info should vary across ARQs but ignored for
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# testing
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"attach_handle_info": {
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"bus": "1",
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"device": "0",
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"domain": "0",
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"function": "0"
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},
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"device_profile_group": {"resources:GPU": "1"}
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}, {
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"state": "Deleting",
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"device_profile_name": "dp_example_2",
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"hostname": "myhost1",
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"instance_uuid": "5922a70f-1e06-4cfd-88dd-a332120d7144",
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"attach_handle_type": "PCI",
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# attach_handle info should vary across ARQs but ignored for
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# testing
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"attach_handle_info": {
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"bus": "2",
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"device": "0",
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"domain": "0",
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"function": "0"
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},
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"device_profile_group": {
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"trait:CUSTOM_FPGA_INTEL": "required",
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"resources:FPGA": "1"}
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}, {
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"state": "Deleting",
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"device_profile_name": "dp_example_3",
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"hostname": "myhost3",
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"instance_uuid": "5922a70f-1e06-4cfd-88dd-a332120d7146",
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"attach_handle_type": "PCI",
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# attach_handle info should vary across ARQs but ignored for
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# testing
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"attach_handle_info": {
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"bus": "3",
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"device": "0",
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"domain": "0",
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"function": "0"
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},
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"device_profile_group": {
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"trait:CUSTOM_FPGA_INTEL": "required",
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"resources:FPGA": "1",
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"accel:bitstream_id": "b069d97a-010a-4057-b70d-eca2b337fc9e"}
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}, {
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"state": "Unbound",
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"device_profile_name": "dp_example_2",
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"hostname": "myhost1",
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"instance_uuid": "5922a70f-1e06-4cfd-88dd-a332120d7144",
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"attach_handle_type": "PCI",
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# attach_handle info should vary across ARQs but ignored for
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# testing
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"attach_handle_info": {
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"bus": "2",
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"device": "0",
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"domain": "0",
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"function": "0"
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},
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"device_profile_group": {
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"trait:CUSTOM_FPGA_INTEL": "required",
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"resources:FPGA": "1"}
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},
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]
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arqs = [ # Corresponds to 1st device profile in fake_device)profile.py
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{"uuid": "a097fefa-da62-4630-8e8b-424c0e3426de",
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"device_profile_group_id": 0,
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"device_rp_uuid": "8787595e-9954-49f8-b5c1-cdb55b59062e",
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},
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{"uuid": "aa140114-4869-45ea-8213-45f530804b0d",
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"device_profile_group_id": 0,
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"device_rp_uuid": "a1ec17f2-0051-4737-bac4-f074d8a01a9d",
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},
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{"uuid": "292b2fa2-0831-484c-aeac-09c794428a5e",
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"device_profile_group_id": 0,
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"device_rp_uuid": "57455a49-bde4-490e-9179-9aa84a3870bb",
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},
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{"uuid": "292b2fa2-0831-484c-aeac-09c794428a5d",
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"device_profile_group_id": 0,
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"device_rp_uuid": "57455a49-bde4-490e-9179-9aa84a3870bc",
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}
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]
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new_arqs = []
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for idx, new_arq in enumerate(arqs):
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new_arq.update(common[idx])
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new_arq.update(id=idx)
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new_arqs.append(new_arq)
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return new_arqs
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def _convert_from_dict_to_obj(arq_dict):
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obj_arq = arq.ARQ()
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for field in arq_dict.keys():
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obj_arq[field] = arq_dict[field]
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obj_extarq = ext_arq.ExtARQ()
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obj_extarq.arq = obj_arq
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obj_extarq.device_profile_group = arq_dict["device_profile_group"]
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return obj_extarq
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def get_fake_extarq_objs():
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arq_list = _get_arqs_as_dict()
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obj_extarqs = list(map(_convert_from_dict_to_obj, arq_list))
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return obj_extarqs
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def get_fake_extarq_resolved_objs():
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arq_list = _get_arqs_resloved_as_dict()
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obj_extarqs = list(map(_convert_from_dict_to_obj, arq_list))
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return obj_extarqs
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def get_fake_extarq_bind_objs():
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arq_list = _get_arqs_bind_as_dict()
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obj_extarqs = list(map(_convert_from_dict_to_obj, arq_list))
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return obj_extarqs
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def _convert_from_dict_to_fpga_obj(arq_dict):
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obj_arq = arq.ARQ()
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for field in arq_dict.keys():
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obj_arq[field] = arq_dict[field]
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obj_extarq = fpga_ext_arq.FPGAExtARQ()
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obj_extarq.arq = obj_arq
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obj_extarq.device_profile_group = arq_dict["device_profile_group"]
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return obj_extarq
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def get_fake_fpga_extarq_objs():
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arq_list = _get_arqs_as_dict()[1:]
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obj_extarqs = list(map(_convert_from_dict_to_fpga_obj, arq_list))
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return obj_extarqs
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def get_fake_db_extarqs():
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db_extarqs = []
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for db_extarq in _get_arqs_as_dict():
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db_extarq.update({'device_profile_id': 0})
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db_extarqs.append(db_extarq)
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return db_extarqs
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def get_fake_fpga_db_extarqs():
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return get_fake_db_extarqs()[1:]
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def get_patch_list(same_device=True):
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"""Returns a list of bindings for many ARQs.
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:param same_device: Flag that the returned bindings for all ARQs
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must be for the same device.
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"""
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arqs = _get_arqs_as_dict()
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host_binding = {'path': '/hostname', 'op': 'add',
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'value': arqs[0]['hostname']}
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inst_binding = {'path': '/instance_uuid', 'op': 'add',
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'value': arqs[0]['instance_uuid']}
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device_rp_uuid = 'fb16c293-5739-4c84-8590-926f9ab16669'
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patch_list = {}
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for newarq in arqs:
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dev_uuid = device_rp_uuid if same_device else newarq['device_rp_uuid']
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dev_binding = {'path': '/device_rp_uuid', 'op': 'add',
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'value': dev_uuid}
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patch_list[newarq['uuid']] = [host_binding, inst_binding, dev_binding]
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return patch_list, device_rp_uuid
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def get_fake_xilinx_fpga_extarq_objs():
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arqs = [
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{"uuid": 'b8c19eb2-e03c-47b4-b7cf-ced6086b2d11',
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"device_profile_group_id": 0,
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"state": "Initial",
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"device_profile_name": "fake_xilinx_fpga_dp",
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"hostname": "myhost",
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"instance_uuid": "5922a70f-1e06-4cfd-88dd-a332120d7144",
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"attach_handle_type": "PCI",
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# attach_handle info should vary across ARQs but ignored for testing
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"attach_handle_info": {
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"bus": "3b",
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"device": "00",
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"domain": "0000",
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"function": "0"
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},
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"device_profile_group": {
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"trait:CUSTOM_FPGA_XILINX": "required",
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"resources:FPGA": "1",
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"trait:CUSTOM_FPGA_PRODUCT_ID_5000": "required"}
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},
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{"uuid": '012955c7-90f9-45a9-bb7d-7c2907d8997f',
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"device_profile_group_id": 1,
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"state": "Initial",
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"device_profile_name": "fake_xilinx_fpga_dp",
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"hostname": "myhost",
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"instance_uuid": "5922a70f-1e06-4cfd-88dd-a332120d7144",
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"attach_handle_type": "PCI",
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# attach_handle info should vary across ARQs but ignored for testing
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"attach_handle_info": {
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"bus": "3b",
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"device": "00",
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"domain": "0000",
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"function": "1"
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},
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"device_profile_group": {
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"trait:CUSTOM_FPGA_XILINX": "required",
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"resources:FPGA": "1",
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"trait:CUSTOM_FPGA_PRODUCT_ID_5000": "required"}
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},
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]
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return list(map(_convert_from_dict_to_obj, arqs))
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