Glossary Updates

Added SDP and AMD EPYC
Added CPPC, DBPM, SVM, and SMT

Change-Id: If7ce2eb9a669750ef414d542255ea3e2f349d917
Signed-off-by: Petsy Mathew <petsy.mathew@windriver.com>

doc/source/introduction/terms.rst

@@ -19,6 +19,13 @@ Bare Metal
   workloads run directly on the operating system which runs directly on
   the hardware).
 
+AMD
+  AMD EPYC is a line of multi-core server CPUs based on AMD's Zen
+  microarchitecture, targeted at the server and embedded system markets. These
+  processors offer very high core counts, large memory capacity, and extensive
+  PCIe connectivity—features that make them well-suited for virtualization,
+  cloud computing, HPC, and large-scale data analytics.
+
 Controller
   A node within a |prod| edge cloud that runs the cloud management software
   (*control plane*). There can be either one or two controller nodes in a
@@ -43,6 +50,13 @@ Controller
  Ceph avoids a single point of failure, a performance bottleneck, and a
  physical limit to its scalability.
 
+Collaborative Processor Performance Control (CPCC)
+  A CPU power-management framework that allows the processor and operating
+  system to work together to determine optimal performance levels. When enabled
+  in BIOS, CPPC allows the OS to send performance requests directly to the
+  processor, enabling finer-grained and more efficient frequency and power
+  control.
+
 Data Network(s)
   Networks attached to pci-passthrough and/or sriov interfaces that are made
   available to hosted containers or hosted |VMs| for pci-passthrough and/or |SRIOV|
@@ -67,6 +81,11 @@ Downgrade
   software, firmware, or operating system to a lower version or an older
   release.
 
+Direct Bus Power Management (DBPM)
+  A BIOS setting that delegates CPU power and frequency scaling control
+  entirely to the operating system. When CPU Power Management is set to
+  DBPM, the operating system controls CPU frequency scaling.
+
 Elliptic Curve Digital Signature Algorithm (ECDSA)
   ECDSA is an asymmetric key encryption algorithm that uses Elliptic curve
   cryptography to produce keys and sign data.
@@ -235,6 +254,18 @@ Shared NIC
   cluster-host, pxeboot and data)
   For more information, see :ref:`sriov-port-sharing`.
 
+Simultaneous Multi-Threading (SMT)
+  A processor technology that allows each physical CPU core to execute multiple
+  threads simultaneously. When SMT is enabled, the CPU exposes additional
+  logical cores to the operating system, increasing parallelism and improving
+  performance for multithreaded workloads.
+
+Secure Virtual Machine (SVM)
+  A hardware virtualization extension that enables the CPU to run virtual
+  machines by providing hardware-assisted virtualization features. When SVM is
+  enabled in BIOS, hypervisors (such as KVM, QEMU, or VMware) can leverage
+  CPU-level virtualization for improved performance and isolation.
+
 StarlingX
   StarlingX is an open source, complete cloud infrastructure software stack
   for the edge used by the most demanding applications in industrial |IoT|,
@@ -254,6 +285,12 @@ Storage
   - Provides |HA| persistent storage for images, virtual volumes (that is,
     block storage), and object storage.
 
+Software-Defined Pin
+  An SDP is a configurable hardware pin on supported NICs that can be assigned
+  specific timing or signaling functions through software control. In PTP/PTS
+  deployments, SDPs commonly carry 1 PPS signals between NICs for
+  hardware-level time synchronization.
+
 Unity XT
   A simple, fast, flexible, and all-inclusive unified storage platform.
 

doc/source/shared/abbrevs.txt

@@ -242,6 +242,7 @@
 .. |SCSI| replace:: :abbr:`SCSI (Small Computer System Interface)`
 .. |SCTP| replace:: :abbr:`SCTP (Stream Control Transmission Protocol)`
 .. |SDO| replace:: :abbr:`SDO (Secure Device Onboard)`
+.. |SDP| replace:: :abbr:`SDP (Software-Defined Pin)`
 .. |SEL| replace:: :abbr:`SEL (System Event Log)`
 .. |SGX| replace:: :abbr:`SGX (Software Guard Extensions)`
 .. |SLA| replace:: :abbr:`SLA (Service Level Agreement)`